import sys
sys.path.append("..")
import pyrtl
from  pyrtl import GPUSim
import or1200_definitions

dw = or1200_definitions.OR1200_OPERAND_WIDTH
aw = or1200_definitions.OR1200_OPERAND_WIDTH

class Or1200RframGeneric(object):
    def __init__(self):
        # self.clk = pyrtl.Input(bitwidth=1, name='clk')
        self.rst = pyrtl.Input(bitwidth=1, name='RframGeneric_rst')

        # Port A
        self.ce_a = pyrtl.Input(bitwidth=1, name='RframGeneric_ce_a')
        self.addr_a = pyrtl.Input(bitwidth=aw, name='RframGeneric_addr_a')
        # self.do_a = pyrtl.Output(bitwidth=dw, name='do_a')

        # Port B
        self.ce_b = pyrtl.Input(bitwidth=1, name='RframGeneric_ce_b')
        self.addr_b = pyrtl.Input(bitwidth=aw, name='RframGeneric_addr_b')
        # self.do_b = pyrtl.Output(bitwidth=dw, name='do_b')

        # Port W
        self.ce_w = pyrtl.Input(bitwidth=1, name='RframGeneric_ce_w')
        self.we_w = pyrtl.Input(bitwidth=1, name='RframGeneric_we_w')
        self.addr_w = pyrtl.Input(bitwidth=aw, name='RframGeneric_addr_w')
        self.di_w = pyrtl.Input(bitwidth=dw, name='RframGeneric_di_w')
        ###########################
        # # self.clk = pyrtl.Input(bitwidth=1, name='clk')
        # self.rst = pyrtl.WireVector(bitwidth=1, name='RframGeneric_rst')
        #
        # # Port A
        # self.ce_a = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_a')
        # self.addr_a = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_a')
        # # self.do_a = pyrtl.Output(bitwidth=dw, name='do_a')
        #
        # # Port B
        # self.ce_b = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_b')
        # self.addr_b = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_b')
        # # self.do_b = pyrtl.Output(bitwidth=dw, name='do_b')
        #
        # # Port W
        # self.ce_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_w')
        # self.we_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_we_w')
        # self.addr_w = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_w')
        # self.di_w = pyrtl.WireVector(bitwidth=dw, name='RframGeneric_di_w')
        ###########################
        # Internal wires and regs
        self.intaddr_a = pyrtl.WireVector(bitwidth=aw) #, name='intaddr_a')
        self.intaddr_b = pyrtl.WireVector(bitwidth=aw) #, name='intaddr_b')
        self.mem = pyrtl.WireVector(bitwidth=dw * 32) #, name='mem')
        self.do_a = pyrtl.WireVector(bitwidth=dw) #, name='do_a')
        self.do_b = pyrtl.WireVector(bitwidth=dw) #, name='do_b')
        self.test_do_a = pyrtl.Output(bitwidth=dw , name='do_a')
        self.test_do_b = pyrtl.Output(bitwidth=dw, name='do_b')

        self.test_do_b<<=self.do_b
        self.test_do_a<<=self.do_a

        # initialize all the parts
        writePort = WritePort()
        readPortA1 = ReadPortA1()
        readPortA2 = ReadPortA2()
        readPortB1 = ReadPortB1()
        readPortB2 = ReadPortB2()

        # establish connection relations for Write port
        self.mem <<= writePort.mem
        # writePort.clk <<= self.clk
        writePort.rst <<= self.rst
        writePort.ce_w <<= self.ce_w
        writePort.we_w <<= self.we_w
        writePort.addr_w <<= self.addr_w
        writePort.di_w <<= self.di_w

        # establish connection relations for Read port A_1
        self.intaddr_a <<= readPortA1.intaddr_a
        # readPortA1.clk <<= self.clk
        readPortA1.rst <<= self.rst
        readPortA1.ce_a <<= self.ce_a
        readPortA1.addr_a <<= self.addr_a

        # establish connection relations for Read port A_2
        self.do_a <<= readPortA2.do_a
        readPortA2.mem <<= self.mem
        readPortA2.intaddr_a <<= self.intaddr_a

        # establish connection relations for Read port B_1
        self.intaddr_b <<= readPortB1.intaddr_b
        # readPortB1.clk <<= self.clk
        readPortB1.rst <<= self.rst
        readPortB1.ce_b <<= self.ce_b
        readPortB1.addr_b <<= self.addr_b

        # establish connection relations for Read port B_2
        self.do_b <<= readPortB2.do_b
        readPortB2.mem <<= self.mem
        readPortB2.intaddr_b <<= self.intaddr_b

class Or1200RframGeneric_wire(object):
    def __init__(self):
        # self.clk = pyrtl.Input(bitwidth=1, name='clk')
        self.rst = pyrtl.WireVector(bitwidth=1, name='RframGeneric_rst')

        # Port A
        self.ce_a = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_a')
        self.addr_a = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_a')
        # self.do_a = pyrtl.Output(bitwidth=dw, name='do_a')

        # Port B
        self.ce_b = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_b')
        self.addr_b = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_b')
        # self.do_b = pyrtl.Output(bitwidth=dw, name='do_b')

        # Port W
        self.ce_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_w')
        self.we_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_we_w')
        self.addr_w = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_w')
        self.di_w = pyrtl.WireVector(bitwidth=dw, name='RframGeneric_di_w')
        ###########################
        # # self.clk = pyrtl.Input(bitwidth=1, name='clk')
        # self.rst = pyrtl.WireVector(bitwidth=1, name='RframGeneric_rst')
        #
        # # Port A
        # self.ce_a = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_a')
        # self.addr_a = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_a')
        # # self.do_a = pyrtl.Output(bitwidth=dw, name='do_a')
        #
        # # Port B
        # self.ce_b = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_b')
        # self.addr_b = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_b')
        # # self.do_b = pyrtl.Output(bitwidth=dw, name='do_b')
        #
        # # Port W
        # self.ce_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_ce_w')
        # self.we_w = pyrtl.WireVector(bitwidth=1, name='RframGeneric_we_w')
        # self.addr_w = pyrtl.WireVector(bitwidth=aw, name='RframGeneric_addr_w')
        # self.di_w = pyrtl.WireVector(bitwidth=dw, name='RframGeneric_di_w')
        ###########################
        # Internal wires and regs
        self.intaddr_a = pyrtl.WireVector(bitwidth=aw)  # , name='intaddr_a')
        self.intaddr_b = pyrtl.WireVector(bitwidth=aw)  # , name='intaddr_b')
        self.mem = pyrtl.WireVector(bitwidth=dw * 32)  # , name='mem')
        self.do_a = pyrtl.WireVector(bitwidth=dw)  # , name='do_a')
        self.do_b = pyrtl.WireVector(bitwidth=dw)  # , name='do_b')


        # initialize all the parts
        writePort = WritePort()
        readPortA1 = ReadPortA1()
        readPortA2 = ReadPortA2()
        readPortB1 = ReadPortB1()
        readPortB2 = ReadPortB2()

        # establish connection relations for Write port
        self.mem <<= writePort.mem
        # writePort.clk <<= self.clk
        writePort.rst <<= self.rst
        writePort.ce_w <<= self.ce_w
        writePort.we_w <<= self.we_w
        writePort.addr_w <<= self.addr_w
        writePort.di_w <<= self.di_w

        # establish connection relations for Read port A_1
        self.intaddr_a <<= readPortA1.intaddr_a
        # readPortA1.clk <<= self.clk
        readPortA1.rst <<= self.rst
        readPortA1.ce_a <<= self.ce_a
        readPortA1.addr_a <<= self.addr_a

        # establish connection relations for Read port A_2
        self.do_a <<= readPortA2.do_a
        readPortA2.mem <<= self.mem
        readPortA2.intaddr_a <<= self.intaddr_a

        # establish connection relations for Read port B_1
        self.intaddr_b <<= readPortB1.intaddr_b
        # readPortB1.clk <<= self.clk
        readPortB1.rst <<= self.rst
        readPortB1.ce_b <<= self.ce_b
        readPortB1.addr_b <<= self.addr_b

        # establish connection relations for Read port B_2
        self.do_b <<= readPortB2.do_b
        readPortB2.mem <<= self.mem
        readPortB2.intaddr_b <<= self.intaddr_b



# Write port
class WritePort(object):
    def __init__(self):
        # self.clk = pyrtl.Input(bitwidth=1, name='clk')
        self.rst = pyrtl.WireVector(bitwidth=1)
        self.ce_w = pyrtl.WireVector(bitwidth=1)
        self.we_w = pyrtl.WireVector(bitwidth=1)
        self.addr_w = pyrtl.WireVector(bitwidth=aw)
        self.di_w = pyrtl.WireVector(bitwidth=dw)

        self.mem = pyrtl.Register(bitwidth=dw * 32)
        
        mem = [i for i in self.mem]
        
        with pyrtl.conditional_assignment:
            with self.rst:
                self.mem.next |= pyrtl.concat(pyrtl.Const(0b0, bitwidth=512),pyrtl.Const(0b0, bitwidth=512))
            with self.ce_w & self.we_w:
                with self.addr_w == pyrtl.Const(0, bitwidth=5):
                    mem[32*0 : 32*0+31+1] = pyrtl.Const(00000000, bitwidth=32) # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(1, bitwidth=5):
                    mem[32*1 : 32*1+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(2, bitwidth=5):
                    mem[32*2 : 32*2+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(3, bitwidth=5):
                    mem[32*3 : 32*3+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(4, bitwidth=5):
                    mem[32*4 : 32*4+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(5, bitwidth=5):
                    mem[32*5 : 32*5+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(6, bitwidth=5):
                    mem[32*6 : 32*6+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(7, bitwidth=5):
                    mem[32*7 : 32*7+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(8, bitwidth=5):
                    mem[32*8 : 32*8+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(9, bitwidth=5):
                    mem[32*9 : 32*931+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(10, bitwidth=5):
                    mem[32*10 : 32*10+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(11, bitwidth=5):
                    mem[32*11 : 32*11+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(12, bitwidth=5):
                    mem[32*12 : 32*12+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(13, bitwidth=5):
                    mem[32*13 : 32*13+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(14, bitwidth=5):
                    mem[32*14 : 32*14+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(15, bitwidth=5):
                    mem[32*15 : 32*15+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(16, bitwidth=5):
                    mem[32*16 : 32*16+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(17, bitwidth=5):
                    mem[32*17 : 32*17+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(18, bitwidth=5):
                    mem[32*18 : 32*18+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(19, bitwidth=5):
                    mem[32*19 : 32*19+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(20, bitwidth=5):
                    mem[32*20 : 32*20+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(21, bitwidth=5):
                    mem[32*21 : 32*21+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(22, bitwidth=5):
                    mem[32*22 : 32*22+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(23, bitwidth=5):
                    mem[32*23 : 32*23+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(24, bitwidth=5):
                    mem[32*24 : 32*24+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(25, bitwidth=5):
                    mem[32*25 : 32*25+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(26, bitwidth=5):
                    mem[32*26 : 32*26+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(27, bitwidth=5):
                    mem[32*27 : 32*27+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(28, bitwidth=5):
                    mem[32*28 : 32*28+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(29, bitwidth=5):
                    mem[32*29 : 32*29+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with self.addr_w == pyrtl.Const(30, bitwidth=5):
                    mem[32*30 : 32*30+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))
                with pyrtl.otherwise:
                    mem[32*31 : 32*31+31+1] = self.di_w # #1
                    self.mem.next |= pyrtl.concat(*reversed(mem))

# Read port A_1
class ReadPortA1(object):
    def __init__(self):
        # self.clk = pyrtl.WireVector(bitwidth=1, name='clk')
        self.rst = pyrtl.WireVector(bitwidth=1)
        self.ce_a = pyrtl.WireVector(bitwidth=1)
        self.addr_a = pyrtl.WireVector(bitwidth=aw)

        self.intaddr_a = pyrtl.WireVector(bitwidth=aw)

        with pyrtl.conditional_assignment:
            with self.rst:
                self.intaddr_a |= pyrtl.Const(0x0, bitwidth=5)  # #1
            with self.ce_a:
                self.intaddr_a |= self.addr_a       # #1

# Read port A
class ReadPortA2(object):
    def __init__(self):
        self.mem = pyrtl.WireVector(bitwidth=dw * 32)
        self.intaddr_a = pyrtl.WireVector(bitwidth=aw)

        self.do_a = pyrtl.WireVector(bitwidth=dw)

        with pyrtl.conditional_assignment:
            with self.intaddr_a == pyrtl.Const(0, bitwidth=5):
                self.do_a |= pyrtl.Const(0x0, bitwidth=32)
            with self.intaddr_a == pyrtl.Const(1, bitwidth=5):
                self.do_a |= self.mem[32*1 : 32*1+31+1]
            with self.intaddr_a == pyrtl.Const(2, bitwidth=5):
                self.do_a |= self.mem[32*2 : 32*2+31+1]
            with self.intaddr_a == pyrtl.Const(3, bitwidth=5):
                self.do_a |= self.mem[32*3 : 32*3+31+1]
            with self.intaddr_a == pyrtl.Const(4, bitwidth=5):
                self.do_a |= self.mem[32*4 : 32*4+31+1]
            with self.intaddr_a == pyrtl.Const(5, bitwidth=5):
                self.do_a |= self.mem[32*5 : 32*5+31+1]
            with self.intaddr_a == pyrtl.Const(6, bitwidth=5):
                self.do_a |= self.mem[32*6 : 32*6+31+1]
            with self.intaddr_a == pyrtl.Const(7, bitwidth=5):
                self.do_a |= self.mem[32*7 : 32*7+31+1]
            with self.intaddr_a == pyrtl.Const(8, bitwidth=5):
                self.do_a |= self.mem[32*8 : 32*8+31+1]
            with self.intaddr_a == pyrtl.Const(9, bitwidth=5):
                self.do_a |= self.mem[32*9 : 32*9+31+1]
            with self.intaddr_a == pyrtl.Const(10, bitwidth=5):
                self.do_a |= self.mem[32*10 : 32*10+31+1]
            with self.intaddr_a == pyrtl.Const(11, bitwidth=5):
                self.do_a |= self.mem[32*11 : 32*11+31+1]
            with self.intaddr_a == pyrtl.Const(12, bitwidth=5):
                self.do_a |= self.mem[32*12 : 32*12+31+1]
            with self.intaddr_a == pyrtl.Const(13, bitwidth=5):
                self.do_a |= self.mem[32*13 : 32*13+31+1]
            with self.intaddr_a == pyrtl.Const(14, bitwidth=5):
                self.do_a |= self.mem[32*14 : 32*14+31+1]
            with self.intaddr_a == pyrtl.Const(15, bitwidth=5):
                self.do_a |= self.mem[32*15 : 32*15+31+1]
            with self.intaddr_a == pyrtl.Const(16, bitwidth=5):
                self.do_a |= self.mem[32*16 : 32*16+31+1]
            with self.intaddr_a == pyrtl.Const(17, bitwidth=5):
                self.do_a |= self.mem[32*17 : 32*17+31+1]
            with self.intaddr_a == pyrtl.Const(18, bitwidth=5):
                self.do_a |= self.mem[32*18 : 32*18+31+1]
            with self.intaddr_a == pyrtl.Const(19, bitwidth=5):
                self.do_a |= self.mem[32*19 : 32*19+31+1]
            with self.intaddr_a == pyrtl.Const(20, bitwidth=5):
                self.do_a |= self.mem[32*20 : 32*20+31+1]
            with self.intaddr_a == pyrtl.Const(21, bitwidth=5):
                self.do_a |= self.mem[32*21 : 32*21+31+1]
            with self.intaddr_a == pyrtl.Const(22, bitwidth=5):
                self.do_a |= self.mem[32*22 : 32*22+31+1]
            with self.intaddr_a == pyrtl.Const(23, bitwidth=5):
                self.do_a |= self.mem[32*23 : 32*23+31+1]
            with self.intaddr_a == pyrtl.Const(24, bitwidth=5):
                self.do_a |= self.mem[32*24 : 32*24+31+1]
            with self.intaddr_a == pyrtl.Const(25, bitwidth=5):
                self.do_a |= self.mem[32*25 : 32*25+31+1]
            with self.intaddr_a == pyrtl.Const(26, bitwidth=5):
                self.do_a |= self.mem[32*26 : 32*26+31+1]
            with self.intaddr_a == pyrtl.Const(27, bitwidth=5):
                self.do_a |= self.mem[32*27 : 32*27+31+1]
            with self.intaddr_a == pyrtl.Const(28, bitwidth=5):
                self.do_a |= self.mem[32*28 : 32*28+31+1]
            with self.intaddr_a == pyrtl.Const(29, bitwidth=5):
                self.do_a |= self.mem[32*29 : 32*29+31+1]
            with self.intaddr_a == pyrtl.Const(30, bitwidth=5):
                self.do_a |= self.mem[32*30 : 32*30+31+1]
            with pyrtl.otherwise:
                self.do_a |= self.mem[32*31 : 32*31+31+1]


# Read port B_1
class ReadPortB1(object):
    def __init__(self):
        # self.clk = pyrtl.WireVector(bitwidth=1, name='clk')
        self.rst = pyrtl.WireVector(bitwidth=1)
        self.ce_b = pyrtl.WireVector(bitwidth=1)
        self.addr_b = pyrtl.WireVector(bitwidth=aw)

        self.intaddr_b = pyrtl.WireVector(bitwidth=aw)

        with pyrtl.conditional_assignment:
            with self.rst:
                self.intaddr_b |= pyrtl.Const(0x0, bitwidth=5)  # #1
            with self.ce_b:
                self.intaddr_b |= self.addr_b       # #1

# Read port B
class ReadPortB2(object):
    def __init__(self):
        self.mem = pyrtl.WireVector(bitwidth=dw * 32)
        self.intaddr_b = pyrtl.WireVector(bitwidth=aw)

        self.do_b = pyrtl.WireVector(bitwidth=dw)

        with pyrtl.conditional_assignment:
            with self.intaddr_b == pyrtl.Const(0, bitwidth=5):
                self.do_b |= pyrtl.Const(0x0, bitwidth=32)
            with self.intaddr_b == pyrtl.Const(1, bitwidth=5):
                self.do_b |= self.mem[32*1 : 32*1+31+1]
            with self.intaddr_b == pyrtl.Const(2, bitwidth=5):
                self.do_b |= self.mem[32*2 : 32*2+31+1]
            with self.intaddr_b == pyrtl.Const(3, bitwidth=5):
                self.do_b |= self.mem[32*3 : 32*3+31+1]
            with self.intaddr_b == pyrtl.Const(4, bitwidth=5):
                self.do_b |= self.mem[32*4 : 32*4+31+1]
            with self.intaddr_b == pyrtl.Const(5, bitwidth=5):
                self.do_b |= self.mem[32*5 : 32*5+31+1]
            with self.intaddr_b == pyrtl.Const(6, bitwidth=5):
                self.do_b |= self.mem[32*6 : 32*6+31+1]
            with self.intaddr_b == pyrtl.Const(7, bitwidth=5):
                self.do_b |= self.mem[32*7 : 32*7+31+1]
            with self.intaddr_b == pyrtl.Const(8, bitwidth=5):
                self.do_b |= self.mem[32*8 : 32*8+31+1]
            with self.intaddr_b == pyrtl.Const(9, bitwidth=5):
                self.do_b |= self.mem[32*9 : 32*9+31+1]
            with self.intaddr_b == pyrtl.Const(10, bitwidth=5):
                self.do_b |= self.mem[32*10 : 32*10+31+1]
            with self.intaddr_b == pyrtl.Const(11, bitwidth=5):
                self.do_b |= self.mem[32*11 : 32*11+31+1]
            with self.intaddr_b == pyrtl.Const(12, bitwidth=5):
                self.do_b |= self.mem[32*12 : 32*12+31+1]
            with self.intaddr_b == pyrtl.Const(13, bitwidth=5):
                self.do_b |= self.mem[32*13 : 32*13+31+1]
            with self.intaddr_b == pyrtl.Const(14, bitwidth=5):
                self.do_b |= self.mem[32*14 : 32*14+31+1]
            with self.intaddr_b == pyrtl.Const(15, bitwidth=5):
                self.do_b |= self.mem[32*15 : 32*15+31+1]
            with self.intaddr_b == pyrtl.Const(16, bitwidth=5):
                self.do_b |= self.mem[32*16 : 32*16+31+1]
            with self.intaddr_b == pyrtl.Const(17, bitwidth=5):
                self.do_b |= self.mem[32*17 : 32*17+31+1]
            with self.intaddr_b == pyrtl.Const(18, bitwidth=5):
                self.do_b |= self.mem[32*18 : 32*18+31+1]
            with self.intaddr_b == pyrtl.Const(19, bitwidth=5):
                self.do_b |= self.mem[32*19 : 32*19+31+1]
            with self.intaddr_b == pyrtl.Const(20, bitwidth=5):
                self.do_b |= self.mem[32*20 : 32*20+31+1]
            with self.intaddr_b == pyrtl.Const(21, bitwidth=5):
                self.do_b |= self.mem[32*21 : 32*21+31+1]
            with self.intaddr_b == pyrtl.Const(22, bitwidth=5):
                self.do_b |= self.mem[32*22 : 32*22+31+1]
            with self.intaddr_b == pyrtl.Const(23, bitwidth=5):
                self.do_b |= self.mem[32*23 : 32*23+31+1]
            with self.intaddr_b == pyrtl.Const(24, bitwidth=5):
                self.do_b |= self.mem[32*24 : 32*24+31+1]
            with self.intaddr_b == pyrtl.Const(25, bitwidth=5):
                self.do_b |= self.mem[32*25 : 32*25+31+1]
            with self.intaddr_b == pyrtl.Const(26, bitwidth=5):
                self.do_b |= self.mem[32*26 : 32*26+31+1]
            with self.intaddr_b == pyrtl.Const(27, bitwidth=5):
                self.do_b |= self.mem[32*27 : 32*27+31+1]
            with self.intaddr_b == pyrtl.Const(28, bitwidth=5):
                self.do_b |= self.mem[32*28 : 32*28+31+1]
            with self.intaddr_b == pyrtl.Const(29, bitwidth=5):
                self.do_b |= self.mem[32*29 : 32*29+31+1]
            with self.intaddr_b == pyrtl.Const(30, bitwidth=5):
                self.do_b |= self.mem[32*30 : 32*30+31+1]
            with pyrtl.otherwise:
                self.do_b |= self.mem[32*31 : 32*31+31+1]


if __name__ == '__main__':
    or1200RframGeneric = Or1200RframGeneric()
    sim = pyrtl.GPUSim_now.GPUSim('rfram')

    com = pyrtl.CompiledSimulation()

    input_width = []
    from pyrtl.wire import Input

    IN = pyrtl.working_block().wirevector_subset(Input)
    for inn in IN:
        name = inn.name
        width = inn.bitwidth
        input_width.append([name, width])
    import random

    max_ = 0
    com_time = 0
    ess_time = 0
    num = 1
    for i in range(num):
        print(i)

        inputs_random = {}
        inputs_select = {}
        inputs_old = {}
        inputs_ = {}

        for inp in input_width:
            inputs_random[inp[0]] = []
            inputs_select[inp[0]] = []
            result = random.randint(0, 2 ** inp[1] - 1)
            inputs_old[inp[0]] = result

        for j in range(131072):
            for inp in input_width:
                result = random.randint(0, 2 ** inp[1] - 1)
                inputs_[inp[0]] = result
                inputs_random[inp[0]].append(result)
            if random.random() < 0.2:
                for name in inputs_old:
                    inputs_select[name].append(inputs_old[name])
            else:
                for name in inputs_:
                    inputs_select[name].append(inputs_[name])
                    inputs_old[name] = inputs_[name]
        time1 = com.step_multiple(inputs_select)

    sim.make_input(inputs_select)